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Push-Pull FET Driver with Integrated Oscillator
and Programmable Clock Output
Pin Description
PIN
1, 8
2
3
4, 14
5
6
7
9
10
11
12
13
EP
NAME
N.C.
SEL1
CLK
I.C.
RT
AGND
DGND
PGND
NDRV1
NDRV2
V CC
SEL2
EP
FUNCTION
No Connection. Must be left unconnected.
CLK Frequency Ratio Select Input. Use SEL1 and SEL2 to set f CLK to f NDRV_ frequency ratio (see Table 1).
Synchronizing Clock Output. Clock output with a ±10mA peak current drive that can be used to synchronize
an external PWM regulator. CLK/NDRV_ frequency has a 1x, 2x, or 4x ratio (see the Synchronizing Clock
Output section).
Connect to ground. Internal function.
Oscillator Timing Resistor Connection. Bypass RT with a series of a 4.7k ? resistor and a 1nF capacitor to
AGND. Connect a resistor from RT to AGND to set the internal oscillator frequency.
Analog Ground. Connect AGND to ground plane.
Digital Ground. Connect DGND to ground plane.
Power Ground. Connect to ground plane.
Gate Driver 1. Connect NDRV1 to the gate of an external n-channel FET.
Gate Driver 2. Connect NDRV2 to the gate of an external n-channel FET.
Power-Supply Input. Bypass V CC to PGND with 0.1μF||1μF ceramic capacitors.
CLK Frequency Divisor Input. Use SEL1 and SEL2 to set f CLK to f NDRV_ frequency ratio (see Table 1).
Exposed Pad. Internally connected to DGND. Connect exposed pad to ground plane.
SEL1
MAX5077
UVLO 3.5V
V CC
SEL2
5V
V CC
NDRV2
DGND
CLK
LDO
Q
Q
Q
Q
T-FF
Q
NDRV1
PGND
Q
INTERNAL
I.C.
RT
OSC
FUNCTION
I.C.
N.C.
AGND
Figure 1. MAX5077 Functional Diagram
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